Process for creating a high density magnetic tunnel junction array test platform

ABSTRACT

A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.

This application is a Divisional of co-pending commonly assigned U.S. patent application Ser. No. 15/992,815, titled “A PROCESS FOR CREATING A HIGH DENSITY MAGNETIC TUNNEL JUNCTION ARRAY TEST PLATFORM” by Pradeep Manandhar, et al., filed on May 30, 2018, and which is incorporated herein in its entirety.

FIELD OF THE INVENTION

Embodiments of the present invention are generally related to the fabrication of integrated circuit structures used in memory systems that can be used by computer systems, including embedded computer systems.

BACKGROUND OF THE INVENTION

Magnetoresistive random-access memory (“MRAM”) is a non-volatile memory technology that stores data through magnetic storage elements. These elements are two ferromagnetic plates or electrodes that can hold a magnetic field and are separated by a non-magnetic material, such as a non-magnetic metal or insulator. This structure is known as a magnetic tunnel junction (MTJ).

MRAM devices can store information by changing the orientation of the magnetization of the free layer of the MTJ. In particular, based on whether the free layer is in a parallel or anti-parallel alignment relative to the reference layer, either a one or a zero can be stored in each MRAM cell. Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell change due to the orientation of the magnetic fields of the two layers. The electrical resistance is typically referred to as tunnel magnetoresistance (TMR) which is a magnetoresistive effect that occurs in a MTJ. The cell's resistance will be different for the parallel and anti-parallel states and thus the cell's resistance can be used to distinguish between a one and a zero. One important feature of MRAM devices is that they are non-volatile memory devices, since they maintain the information even when the power is off.

MRAM devices are considered as the next generation structures for a wide range of memory applications. MRAM products based on spin torque transfer switching are already making its way into large data storage devices. Spin transfer torque magnetic random access memory (STT-MRAM), or spin transfer switching, uses spin-aligned (polarized) electrons to change the magnetization orientation of the free layer in the magnetic tunnel junction. In general, electrons possess a spin, a quantized number of angular momentum intrinsic to the electron. An electrical current is generally unpolarized, e.g., it consists of 50% spin up and 50% spin down electrons. Passing a current though a magnetic layer polarizes electrons with the spin orientation corresponding to the magnetization direction of the magnetic layer (e.g., polarizer), thus produces a spin-polarized current. If a spin-polarized current is passed to the magnetic region of a free layer in the MTJ device, the electrons will transfer a portion of their spin-angular momentum to the magnetization layer to produce a torque on the magnetization of the free layer. Thus, this spin transfer torque can switch the magnetization of the free layer, which, in effect, writes either a one or a zero based on whether the free layer is in the parallel or anti-parallel states relative to the reference layer.

The fabrication of MRAM involves the formation of small MTJ (Magnetic Tunnel Junction) patterns in pillar shapes. The pillars or pillar structures can be patterned on a hard mask layer and then transferred to MTJ films. The patterning of pillars on a hard mask layer is traditionally done using an electron beam lithography in a research environment. However, for high volume production, electron beam patterning is not cost effective as the process is very slow. Alternately, these pillars can be patterned using optical lithography tools. Optical lithography resolution is limited by diffraction. Since the pillars, when printed onto a layer of photoresist, are two dimensional features, it is more challenging to achieve the same resolution as the resolution can be achieved by an 1D pattern such as a line.

Currently, MRAM devices are reported at 28 nm node with a bitcell size of, for example, 0.12 μm². Although active MTJ pillar size can be reduced well below 100 nm, the pitch between MTJ devices is limited by individual bitcell size. Consequently, the pitch between CMOS bitcells need to be much larger than the achievable pitch between active MTJ device pillars. This hinders developing a high density MRAM memory with smaller active MTJ device arrays at higher density. With current research to develop, for example, sub 50 nm active MTJ devices, it will become difficult to have a test platform to test state of the art MTJ devices.

Thus what is needed is a fabrication process that will produce a state-of-the-art high density MTJ pillar array to create a test platform to test state of the art MTJ devices. What is further needed is a fabrication process that will produce a state-of-the-art high density MTJ pillar array. Additionally, existing CMOS design configurations need to be utilized without having to invest to develop new CMOS test platform fabrication processes.

SUMMARY OF THE INVENTION

Embodiments of the present invention implement a method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. Embodiments of the present invention implement a fabrication process that will produce a state-of-the-art high density MTJ pillar array to create a test platform to test state-of-the-art MTJ devices. Embodiments of the present invention implement a fabrication process that will produce a state-of-the-art high density MTJ pillar array. Additionally, embodiments of the present invention advantageously utilize existing CMOS design configurations without having to invest to develop new CMOS test platform fabrication processes.

In one embodiment the present invention is implemented as a method for a photo and electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.

In this manner, the pillar array test device described above has two primary areas of density. The first area density is the density of the bit cells in the grid of bit cells. The second area density is the density of the magnetic tunnel junction pillars produced on the centrally located bit cell. The second area density is much higher than the first area density. Each of the bit cells has to have at least a minimum pitch width between them in order to be manufacturable. In a normal functioning device, there is one magnetic tunnel junction pillar manufactured on each bit cell. Thus the density of the bit cells becomes the density of the magnetic tunnel junction pillars. With the pillar array test device of the present invention, the magnetic tunnel junction pillars are fabricated all on the centrally located bit cell and then conductive traces are used to link each individual magnetic tunnel junction pillar to a respective bit cell of the grid.

The purpose of producing such a device is to simulate magnetic tunnel junction pillar density that may be available 2 to 3 generations of CMOS fabrication processes later. The pillar array test device enables a manufacturer to test magnetic interactions between adjacent magnetic tunnel junction pillars in a high density array. The pillar array test device enables the study and characterization of any electromagnetic interference that may occur between the pillars. This allows intensive preparation for next generations of MRAM device manufacture.

In one embodiment, the plurality of top electrode traces connect to the bit cells in the grid using vias.

In one embodiment, an array of metal posts are fabricated on top of the plurality of bottom electrode pads to function as a base for the array of magnetic tunnel junction pillars.

In one embodiment, each of the plurality of bottom electrode traces comprises tantalum nitride. In one embodiment, each of the plurality of top electrode traces comprises tantalum nitride.

In one embodiment, each of the plurality of bit cells further comprises a CMOS driving transistor for individually addressing each of the magnetic tunnel junction pillars.

In one embodiment, a silicon oxide passivation layer is deposited on the surface of the wafer.

In one embodiment, the present invention is implemented as a pillar array test device. The device includes a grid of bit cells having a first density, and an array of magnetic tunnel junction pillars fabricated on a centrally located bit cell having a second density that is higher than the first density. The device further includes a bottom electrode layer connecting each of the magnetic tunnel junction pillars to a respective one of the grid of bit cells in a first fanout pattern, and a top electrode layer connecting each of the magnetic tunnel junction pillars to a respective one of the grid of bit cells in a second fanout pattern.

In one embodiment the present invention is implemented as a method for a fabricating process for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid having a first density wherein each of the plurality of bit cells further comprises a CMOS driving transistor, and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell and having a second density higher than the first density, and planarizing the wafer. The method concludes by etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.

In this manner, embodiments of the present invention implement a method for a photo and electron beam lithographic fabricating processes for producing a pillar array test device. Embodiments of the present invention implement a fabrication process that will produce a state-of-the-art high density MTJ pillar array to create a test platform to test state-of-the-art MTJ devices. Embodiments of the present invention implement a fabrication process that will produce a state-of-the-art high density MTJ pillar array. Additionally, embodiments of the present invention advantageously utilizes existing CMOS design configurations without having to invest to develop new CMOS test platform fabrication processes.

Embodiments of the present invention provide the advantage that the new development in MRAM devices can be independently experimented and tested without having to invest significant effort into developing new CMOS platform used in addressing the MRAM devices. The time and cost to develop new CMOS platforms is many orders of magnitude higher than the approach of the embodiments of the present invention.

The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements.

FIG. 1 shows the steps of a process for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device in accordance with one embodiment of the present invention.

FIG. 2A shows the steps of a process for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device in accordance with one embodiment of the present invention.

FIG. 2B shows the steps of a process for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device in accordance with one embodiment of the present invention.

FIG. 3 shows the steps of a process for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device in accordance with one embodiment of the present invention.

FIG. 4 shows a flowchart of the steps of a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device.

DETAILED DESCRIPTION

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of embodiments of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the embodiments of the present invention.

A Process for Creating a High Density Magnetic Tunnel Junction Array Test Platform

Embodiments of the present invention implement a method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. Embodiments of the present invention implement a fabrication process that will produce a state-of-the-art high density MTJ pillar array to be used as a test platform to test state-of-the-art MTJ devices. Embodiments of the present invention implement a fabrication process that will produce a state-of-the-art high density MTJ pillar array. Additionally, embodiments of the present invention advantageously utilize existing CMOS design configurations without having to invest to develop new CMOS test platform fabrication processes.

In one embodiment the present invention is implemented as a method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. By fabricating each of the magnetic tunnel junction pillars on the centrally located bit cell, as opposed to one magnetic tunnel junction pillar per bit cell, a very high density between adjacent magnetic tunnel junction pillars is achieved. This density is generally 2 to 3 generations of CMOS manufacturing equipment higher than what could normally be achieved. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.

In this manner, the pillar array test device described above has two primary areas of density. The first area density is the density of the bit cells in the grid of bit cells. The second area density is the density of the magnetic tunnel junction pillars produced on the centrally located bit cell. Each of the bit cells has to have at least a minimum pitch width between them in order to be manufacturable. This limits the achievable density of the grid of bit cells to what is referred as a first level of density. In a normal functioning device, there is one magnetic tunnel junction pillar manufactured on each bit cell. Thus the density of the bit cells becomes the density magnetic tunnel junction pillars. With the pillar array test device of the present invention described above, the magnetic tunnel junction pillars are fabricated all on the centrally located bit cell. This achieves a second level of density of the magnetic tunnel junction pillars that is much higher than the first level of density of the grid of bit cells. Once the magnetic tunnel junction pillars are fabricated, conductive traces are used to link each individual magnetic tunnel junction pillar to a respective bit cell of the grid.

The purpose of producing such a device is to simulate magnetic tunnel junction pillar density that may be available 2 to 3 generations of CMOS fabrication processes later. The pillar array test device enables a manufacturer to test magnetic interactions between adjacent magnetic tunnel junction pillars in a high density array. The magnetic tunnel junction pillars are addressed and read or written to in a conventional manner (e.g., bit lines, source lines, word lines, etc.). The pillar array test device enables the study and characterization of any electromagnetic interference that may occur between the pillars. This allows intensive preparation for next generations of MRAM device manufacture.

Embodiments of the present invention provide the advantage that the new development in MRAM devices can be independently experimented and tested without having to invest significant effort into developing a new CMOS platform used in addressing the MRAM devices. The time and cost to develop a new CMOS platforms is many orders of magnitude higher than the approach of the embodiments of the present invention. The magnetic interactions between a high density array of adjacent magnetic tunnel junction pillars and electronic interference that may occur between them can be closely tested and studied. This allows intensive preparation for next generations of MRAM device manufacture.

FIG. 1 shows the steps of a process 100 for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device in accordance with one embodiment of the present invention. Process 100 begins in step 102 where a CMOS platform wafer is received for processing. As shown in step 102, the wafer includes a plurality of rectangular bit cells arranged in a grid. These bit cells are at a relatively low density since the bit cells cannot be manufactured below a minimum pitch width. These bit cells each include a driving transistor for connecting to a respective magnetic tunnel junction. The wafer is received with a top layer of silicon oxide for passivation. In step 104, a plurality of metal posts are fabricated for each individual bottom electrode pad and then planarized. A plurality of bottom electrode traces are then etched to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. Instead of locating a single MTJ device in a single bit cell, embodiments of the present invention will position multiple MTJ devices on a single centrally located bit cell. A multilayer lithographic technique will be used to fabricate metal traces to connect individual MTJ devices to individual bit cells and the associated CMOS driving transistor. In one embodiment, each of the plurality of bottom electrode traces comprises tantalum nitride.

In step 106, metal pads are fabricated from each individual bottom electrode pad and then planarized as shown. Additionally, an iterative process is utilized to fabricate metal lines to connect individual MTJ devices to individual bit cells and the associated CMOS driving transistor, creating a fan out pattern 107 as shown.

FIG. 2A shows the steps of a process 200 for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device in accordance with one embodiment of the present invention. Step 202 shows the wafer with the front of CMOS platform having silicon oxide passivation on top. This is basically the wafer as it appears at the conclusion of step 106 of FIG. 1. In step 204, an additional number of bottom electrode traces are fabricated to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. This is shown by the fan out of traces which each route towards the centrally located bit cell. In step 206, new metal posts are created on the centrally located bottom electrode pad to serve as a base for subsequently manufactured magnetic tunnel junction pillars. After the posts have been fabricated, the wafer is planarized.

FIG. 2B shows enlarged views 210 and 212 showing the connections of the high density pillars and the fan out of traces which each route outward to connect to the respective bit cells. In this manner, the high-density pillars having density much higher than the density of the grid of bit cells. Since each of the pillars must still be connected to a respective one of the bit cells, the fan out pattern shown in views 210 and 212 are used to implement the connections.

FIG. 3 shows the steps of a process 300 for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device in accordance with one embodiment of the present invention. Step 302 shows wafer after the magnetic tunnel junction stack deposition layers are deposited. Step 304 shows the ion beam etching of HDP (high-density pillar) magnetic tunnel junction pillar arrays after electron beam lithography. It should be noted that the density of the pillar array is much higher than the density of the grid of bit cells. Step 306 shows how a plurality of top electrode traces fanning out to connect the plurality of magnetic tunnel junction pillars in the centrally located bit cell to each of the bit cells in the grid. The wafer is now ready for outputting for subsequent testing. In one embodiment, the plurality of top electrode traces connect to the bit cells in the grid using vias. In one embodiment, each of the plurality of top electrode traces comprises tantalum nitride.

It should be noted that each of the steps 102 through 106, 202 through 206, and 302 through 306 are implemented using conventional CMOS fabrication techniques on conventional CMOS equipment. By fabricating the HDP magnetic tunnel junction pillar array in the centrally located cell, very high magnetic tunnel junction densities are achieved. Since each magnetic tunnel junction pillar is connected to its own respective bit cell from the bottom electron traces and the top electron traces, each magnetic tunnel junction pillar is individually addressable for testing using a lower density bit cell array. The HDP magnetic tunnel junction pillar array allows testing to examine the effects of magnetic fields from closely adjacent magnetic tunnel junction pillars, for example.

In this manner, embodiments of the present invention implement a method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. Embodiments of the present invention implement a fabrication process that will produce a state-of-the-art high density MTJ pillar array to create a test platform to test state-of-the-art MTJ devices. Embodiments of the present invention implement a fabrication process that will produce a state-of-the-art high density MTJ pillar array. Additionally, embodiments of the present invention advantageously utilizes existing CMOS design configurations without having to invest to develop new CMOS test platform fabrication processes.

FIG. 4 shows a flowchart of the steps of a photo and/or electron beam lithographic fabricating processes 400 for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. In step 401, process 400 begins with receiving a wafer having a plurality of bit cells arranged in a grid. In step 402, process 400 proceeds with etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. In step 403, process 400 proceeds with fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. In step 404, the wafer is then planarized. In step 405, process 400 proceeds with etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid. In step 406, the wafer is output for subsequent testing.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents. 

What is claimed is:
 1. A device, comprising: a grid of bit cells having a first density; an array of pillars fabricated on a centrally located bit cell having a second density that is higher than the first density; a bottom electrode layer comprising a plurality of bottom electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a first fanout pattern; and a top electrode layer comprising a plurality of top electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a second fanout pattern.
 2. The device of claim 1, wherein the plurality of top electrode traces connect to the bit cells in the grid using vias.
 3. The device of claims 1, further comprising an array of metal posts located on top of the plurality of bottom electrode traces and operable to function as a base for the array of memory cell pillars.
 4. The device of claim 1, wherein each of the plurality of bottom electrode traces comprises tantalum nitride.
 5. The device of claim 1, wherein each of the plurality of top electrode traces comprises tantalum nitride.
 6. The device of claim 1, wherein each of the grid of bit cells further comprises a CMOS driving transistor for individually addressing each of the memory cell pillars.
 7. The device of claim 1, further comprising a silicon oxide passivation layer on the surface of the device.
 8. A device, comprising: a grid of bit cells having a first density; an array of memory cell pillars fabricated on a centrally located bit cell having a second density that is higher than the first density; a bottom electrode layer comprising of a plurality of bottom electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a first fanout pattern; a top electrode layer comprising a plurality of top electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a second fanout pattern; and a silicon oxide passivation layer on the surface of the device.
 9. The device of claim 8, wherein the plurality of top electrode traces connect to the bit cells in the grid using vias.
 10. The device of claim 8, further comprising an array of metal posts located on top of the plurality of bottom electrode traces and function as a base for the array of memory cell pillars.
 11. The device of claim 8, wherein each of the plurality of bottom electrode traces comprises tantalum nitride.
 12. The device of claim 8, wherein each of the plurality of top electrode traces comprises tantalum nitride.
 13. The device of claim 8, wherein each of the grid of bit cells further comprises a CMOS driving transistor for individually addressing each of the memory cell pillars.
 14. A device, comprising: a grid of bit cells having a first density; an array of memory cell pillars fabricated on a centrally located bit cell having a second density that is higher than the first density; a bottom electrode layer comprising a plurality of bottom electrode traces connecting each of the memory cell pillars to a respective one of the grid of bit cells in a first fanout pattern; a top electrode layer comprising a plurality of top electrode traces connecting each of the memory cell to a respective one of the grid of bit cells in a second fanout pattern; and a CMOS driving transistor for individually addressing each of the memory cell pillars.
 15. The device of claim 14, wherein the plurality of top electrode traces connect to the bit cells in the grid using vias.
 16. The device of claim 14, wherein an array of metal posts are located on top of the plurality of bottom electrode traces and function as a base for the array of memory cell pillars.
 17. The device of claim 14, wherein each of the plurality of bottom electrode traces comprises tantalum nitride.
 18. The device of claim 14, wherein each of the plurality of top electrode traces comprises tantalum nitride.
 19. The device of claim 14, further comprising a silicon oxide passivation layer on the surface of the device.
 20. The device of claim 14, further comprising a plurality of contact points operable to interface with a CMOS testing device.
 21. The device of claim 14, wherein the device comprises a pillar array test device.
 22. The device of claim 14, wherein the memory cell pillars comprise magnetic tunnel junction pillars.
 23. The device of claim 1, wherein the memory cell pillars comprise magnetic tunnel junction pillars.
 24. The device of claim 8, wherein the memory cell pillars comprise magnetic tunnel junction pillars. 